This application is based upon and claims priority of Japanese Patent Application No. 2001-67049, filed on Mar. 9, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The invention relates to an A/D converter for converting an input analog signal into a digital signal.
2. Description of the Related Art
With the rapid progress of digital signal processing technologies in recent years, sophistication is increasingly demanded of A/D converters which are the interfaces with analog circuits. Among high-speed, low-power configurations of A/D converters is an interpolation type two-stage serial parallel scheme.
FIG. 18 shows the configuration of a two-stage serial parallel type A/D converter described in Japanese Patent Laid-Open Publication No.Hei 3-157020. This A/D converter is a two-stage serial parallel type A/D converter which utilizes interpolation to perform A/D conversion in two stages consisting of an upper A/D conversion block 1831 and a lower A/D conversion block 1832.
The A/D converter comprises a reference voltage generating circuit 1801 composed of a series of resistors, a differential amplifier row 1802, a sample/hold (S/H) circuit row 1803, comparator rows 1804 and 1812, a switch row 1805, an upper encoder 1806, S/H circuits 1807 and 1808, differential amplifiers 1809 and 1810, a resistive interpolation circuit 1811, and a lower encoder 1813.
Initially, in the upper A/D conversion block 1831, the differential voltages between individual reference voltages obtained from the reference voltage generating circuit 1801 and an analog input voltage are amplified by the differential amplifier row 1802. The differential voltages are sampled/held by the S/H circuit row 1803. The differential voltages held by the S/H circuit row 1803 are compared in the comparator row 1804. The outputs of the comparator row 1804 are converted into binary digital code by the upper encoder 1806, obtaining an upper A/D conversion result 1821.
At the same time, the upper encoder 1806 generates a control signal CTL for turning on certain switches in the switch row 1805, so that differential voltages with two reference voltages in the vicinity of the input voltage, out of the differential voltages held by the S/H circuit row 1803 are transferred to the lower A/D conversion block 1832. The two differential voltages transferred are sampled/held by the S/H circuits 1807 and 1808. The noninverted outputs and inverted outputs of the differential amplifiers 1809 and 1810 are individually interpolated by the resistive interpolation circuit 1811. The resulting interpolated voltages are compared in the comparator row 1812. The lower encoder 1813 converts the outputs of the comparator row 1812 into binary digital code to obtain a lower A/D conversion result 1822.
Hereinafter, description will be given in conjunction with an operation timing chart of FIG. 19. A signal 1901 is a signal of the S/H circuit row 1803. A signal 1902 is a signal of the comparator row 1804. A signal 1903 is a signal of the selector switch 1805. A signal 1904 is a signal of the S/H circuits 1807 and 1808. A signal 1905 is a signal of the comparator row 1812. The signals 1901 and 1902 are signals 1911 of the upper A/D conversion block 1831. The signals 1904 and 1905 are signals 1912 of the lower A/D conversion block 1832. A conversion cycle 1921 of the A/D converter is the sum of period a1, b1, and c1.
The S/H circuit row 1803, after a sample mode in the period a1, changes from the sample mode to a hold mode. The held voltage is settled in the period b1. The comparator row 1804 starts its comparing operation in the period b1, and outputs the result in the period c1. At the same time, the encoder 1806 generates the upper A/D conversion result 1821 and a control signal CTL from the comparison outputs, and keeps certain switches 1805 on over the period c1. During the period c1 in which differential voltages are transferred from the upper A/D conversion block 1831 to the lower A/D conversion block 1832, the S/H circuits 1807 and 1808 are in a sample mode. The S/H circuits 1807 and 1808 change to a hold mode in the period a2.
On the other hand, at the period a2, the S/H circuit row 1803 returns to the sample mode. In the lower A/D conversion block 1832, the outputs of the interpolation circuit 1811 are settled in the period a2 before the comparator row 1812 starts its comparing operation. From the comparisons, the encoder 1813 outputs the lower A/D conversion result 1822 at the period b 2. It is the operating speed of the S/H circuit row 1803 that determines the conversion speed (sampling frequency) of the A/D converter. Thus, as shown in FIG. 19, the sum of the periods a1, b1, and c1 fixes the conversion cycle of this A/D converter.
In the interpolation type two-stage serial parallel scheme, the following three points are important, in terms of operating timing, to prevent a deterioration in conversion accuracy:
(1) Start the comparing operation of the comparator rows 1804 only after the S/H circuit row 1803 is sufficiently settled and stabilized in hold voltage.
(2) Secure longer time (period c1) for transferring differential voltages from the upper A/D conversion block 1831 to the lower A/D conversion block 1832 so that the S/H circuits 1807 and 1808 can well follow in sampling operation.
(3) Set the timing to turn off the switches 1805 for transferring differential voltages from the upper A/D conversion block 1831 to the lower A/D conversion block 1832 in advance of switching the S/H circuit row 1803 from the hold mode to the sample mode.
The interpolation type two-stage serial parallel scheme shown in FIG. 18 has the following problems. A rise in the number of bits to be converted in the lower stage increases the number of interpolation nodes by power of 2. In each interpolation node, the settling time of the interpolation voltage is determined by the time constant between the load capacitance and the interpolation resistance of that interpolation node. The greater the number of bits to be converted in the lower stage, the slower the operating speed of the interpolation circuit becomes. At higher conversion speeds, the interpolating operations therefore fail to follow the changes of the differential voltages transferred from the upper A/D conversion block, deteriorating the conversion accuracy in the lower stage.
From the foregoing it will be seen that when a high-speed high-resolution A/D converter is to be configured as shown in FIG. 18, the number of bits to be converted at the lower stage is appropriately set to a smaller value (no greater than 3 bits) so as to suppress an interpolation-originated deterioration in conversion accuracy. Nevertheless, due to its two-stage configuration consisting of upper and lower stages, the serial parallel type ends up requiring a greater number of bits in upper stage A/D conversion, to constitute a high-resolution A/D converter. This spoils the advantages of the serial parallel type over a full flash type, such as smaller parts numbers and a reduction in power consumption.
The S/H circuit row 1803 must remain in the hold mode until differential voltages are transferred to the lower A/D conversion block completely. This fixes the conversion speed of the A/D converter as shown in FIG. 19.
On the other hand, the comparator row 1804 starts comparisons in the period b1. This comparison start timing is preferably set as close to the end of period b1 as possible, considering the sufficient settling of the hold voltages in the S/H circuit row 1803. In reality, however, the encoder 1806 inevitably has a circuit-operation delay time before generating the control signal CTL for the switches 1805 out of the comparison outputs of the comparator row 1804. Therefore, if the comparison start timing is set too closer to the end of the period b1, the switches 1805 for transferring the differential voltages from the upper A/D conversion block 1831 to the lower A/D conversion block 1832 come to be turned on in the middle of the period c1, with a reduction in the actual transfer time. When the transfer time becomes shorter than the acquisition time of the S/H circuits 1807 and 1808, the differential voltages to be transferred to the lower A/D conversion block 1832 may not be settled sufficiently, contributing to a deterioration in the conversion accuracy of the lower A/D conversion block 1832.
From the foregoing it will be seen that the hold time of the S/H circuit row 1803, for the sake of preventing a deterioration in conversion accuracy, must be made longer than the sum total of the settling time of the hold voltages in the S/H circuit row 1803, the operation delay time of the encoder 1806, and the acquisition time of the S/H circuits 1807 and 1808 in the lower A/D conversion block 1832. This determines the conversion speed with respect to conversion accuracy.
Primary factors for integral nonlinear errors of the A/D converter are input/output nonlinear errors occurring in a differential amplifier row that lies in the input front end of the A/D converter, and input offset voltages. Of these, the nonlinear errors can be reduced by adjusting bias current and transistor size.
In contrast, the offset voltages occur in a random fashion due to such reasons as element variations and asymmetry in layout, and still vary by several to ten-odd millivolts even if the transistors are designed with greater size. At higher resolutions or low-power-voltage operations, A/D converters have an LSB as extremely small as several millivolts. Thus, the input offset voltages can easily deteriorate the conversion accuracy. Therefore, the correction of the input offset voltages leads to higher accuracy.
It is an object of the present invention to provide an A/D converter of higher speed.
Another object of the present invention is to provide an A/D converter of higher accuracy.
Still another object of the present invention is to provide an A/D converter of lower power consumption.
An A/D converter according to the presetn invention comprises: a reference voltage generating circuit for generating a plurality of reference voltages; a differential amplifier row including a plurality of differential amplifiers for receiving an analog input voltage at one input terminals and the individual reference voltages generated by the reference voltage generating circuit at the other input terminals, amplifying differential voltages between the analog input voltage and the individual reference voltages while maintaining positive/negative signs thereof, and outputting the resultant to between noninverted output terminals and inverted output terminals as potential differences; a first sample/hold circuit row including a plurality of first sample/hold circuits for sampling/holding the individual differential voltages output from the differential amplifier row; a second sample/hold circuit row for performing interleaving operations, having a pair of second and third sample/hold circuits connected to each output of the first sample/hold circuit row; a first comparator row including a plurality of comparators for determining whether the individual differential voltages held by the first sample/hold circuit row are positive or negative; and a first encoder for outputting digital code corresponding to the outputs of the first comparator row.
The second sample/hold circuit row includes the second and third sample/hold circuits which are connected in parallel to each output of the first sample/hold circuit row. When the second sample/hold circuits are in a sample mode, the third sample/hold circuits are brought into a hold mode so that the sample/hold circuits for sampling are alternated at conversion cycles. The alternation of the sample/hold circuits for sampling allows an increase in A/D conversion speed. Since stable hold time can be secure, it is possible to realize an A/D converter of higher accuracy.